A Reconfigurable Architecture for Secure Multimedia Delivery

This paper introduces a reconfigurable architecture for ensuring secure and real-time video delivery through a novel parameterized construction of the Discrete Wavelet Transform (DWT). This parameterized construction promises multimedia encryption and is also well-suited to a hardware implementation due to our derivation of rational filter coefficients. We achieve an efficient and high-throughput reconfigurable hardware implementation through the use of LUT-based constant multipliers enabling run-time reconfiguration of encryption key. We also compare our prototype (using a Xilinx Virtex 4 FPGA) to several existing implementations in the research literature and show that we achieve superior performance as compared to both traditional CPU-based and custom VLSI approaches while adding features for secure multimedia delivery.

• Type: Journal
• Year: 2010
• Where: VLSID
• Authors: Amit Pande, Joseph Zambreno
• Keywords: Discrete Wavelet Transform, Hardware Implementation, Rational Filter Coefficients, VLSI, VLSID 2010