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2010
IEEE

A reconfigurable cache memory with heterogeneous banks

9 years 8 months ago
A reconfigurable cache memory with heterogeneous banks
Abstract— The optimal size of a large on-chip cache can be different for different programs: at some point, the reduction of cache misses achieved when increasing cache size hits diminishing returns, while the higher cache latency hurts performance. This paper presents the Amorphous Cache (AC), a reconfigurable L2 on-chip cache aimed at improving performance as well as reducing energy consumption. AC is composed of heterogeneous sub-caches as opposed to common caches using homogenous subcaches. The sub-caches are turned off depending on the application workload to conserve power and minimize latencies. A novel reconfiguration algorithm based on Basic Block Vectors is proposed to recognize program phases, and a learning mechanism is used to select the appropriate cache configuration for each program phase. We compare our reconfigurable cache with existing proposals of adaptive and non-adaptive caches. Our results show that the combination of AC and the novel reconfiguration algorithm ...
Domingo Benitez, Juan C. Moure, Dolores Rexachs, E
Added 10 Jul 2010
Updated 10 Jul 2010
Type Conference
Year 2010
Where DATE
Authors Domingo Benitez, Juan C. Moure, Dolores Rexachs, Emilio Luque
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