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2008
ACM

A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip

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A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip
In this paper we present a reconfigurable routing algorithm for a 2D-Mesh Network-on-Chip (NoC) dedicated to faulttolerant, Massively Parallel Multi-Processors Systems on Chip (MP2-SoC). The routing algorithm can be dynamically reconfigured, to adapt to the modification of the micro-network topology caused by a faulty router. This algorithm has been implemented in a reconfigurable version of the DSPIN micro-network, and evaluated from the point of view of performance (penalty on the network saturation threshold), and cost (extra silicon area occupied by the reconfigurable version of the router). Categories and Subject Descriptors B.8.1 [PERFORMANCE AND RELIABILITY]: Re
Zhen Zhang, Alain Greiner, Sami Taktak
Added 12 Nov 2009
Updated 12 Nov 2009
Type Conference
Year 2008
Where DAC
Authors Zhen Zhang, Alain Greiner, Sami Taktak
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