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9

DFT
1994
IEEE

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Reconfiguration in 3D Meshes

13 years 8 months ago

Reconfiguration in 3D Meshes

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The 1: track model for fault tolerant 2 0 processor arrays is extended to 30 mesh architectures. Non-intersecting, continuous, straight and non-near miss compensation paths are considered. It is shown that when six directions in the 30 mesh are allowed for compensation paths, then switches with 13 states are needed to preserve the 30 mesh topology after faults. It is also shown that switch reconfiguration after faults is local in the sense that the state of each switch is uniquely determined by the state of the 2 processors connected to it.

Anuj Chandra, Rami G. Melhem

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Added	08 Aug 2010
Updated	08 Aug 2010
Type	Conference
Year	1994
Where	DFT
Authors	Anuj Chandra, Rami G. Melhem

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