Sciweavers

Share
FPL
2006
Springer

Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAs

9 years 11 months ago
Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAs
As manufacturing technology enters the ultra-deep submicron era, wafer yields are destined to drop due to higher occurrence of physical defects on the die. This paper proposes a yield enhancement scheme based on the use of spare interconnect resources in each routing channel to tolerate functional faults. By using a node-covering technique and integer-linear programming (ILP) methods, the scheme is shown to provide minimal area and timing overheads. Significant yield improvements can thus be achieved.
Nicola Campregher, Peter Y. K. Cheung, George A. C
Added 22 Aug 2010
Updated 22 Aug 2010
Type Conference
Year 2006
Where FPL
Authors Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko
Comments (0)
books