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1999
IEEE

The Recursive Grid Layout Scheme for VLSI Layout of Hierarchical Networks

9 years 5 months ago
The Recursive Grid Layout Scheme for VLSI Layout of Hierarchical Networks
We propose the recursive grid layout scheme for deriving efficient layouts of a variety of hierarchical networks and computing upper bounds on the VLSI area of general hierarchical networks. In particular, we construct optimal VLSI layouts for butterfly networks, generalized hypercubes, and star graphs that have areas within a factor of 1 + o1 from their lower bounds. We also derive efficient layouts for a number of other important networks, such as cubeconnected cycles (CCC) and hypernets, which are the best results reported for these networks thus far.
Chi-Hsiang Yeh, Behrooz Parhami, Emmanouel A. Varv
Added 03 Aug 2010
Updated 03 Aug 2010
Type Conference
Year 1999
Where IPPS
Authors Chi-Hsiang Yeh, Behrooz Parhami, Emmanouel A. Varvarigos
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