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2008
ACM

Reducing the impact of intra-core process variability with criticality-based resource allocation and prefetching

8 years 4 months ago
Reducing the impact of intra-core process variability with criticality-based resource allocation and prefetching
We develop architectural techniques for mitigating the impact of process variability. Our techniques hide the performance effects of slow components--including registers, functional units, and L1I and L1D cache frames--without slowing the clock frequency or pessimistically assuming that all components are slow. Using ideas previously developed for other purposes--criticality-based allocation of resources, prefetching, and prefetch buffering--we allow design engineers to aggressively set the clock frequency without worrying about the subset of components that cannot meet this frequency. Our techniques outperform speed binning, because clock frequency benefits outweigh slight losses in IPC. Categories and Subject Descriptors
Bogdan F. Romanescu, Michael E. Bauer, Sule Ozev,
Added 12 Oct 2010
Updated 12 Oct 2010
Type Conference
Year 2008
Where CF
Authors Bogdan F. Romanescu, Michael E. Bauer, Sule Ozev, Daniel J. Sorin
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