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Reducing Ownership Overhead for Load-Store Sequences in Cache-Coherent Multiprocessors

10 years 4 months ago
Reducing Ownership Overhead for Load-Store Sequences in Cache-Coherent Multiprocessors
Parallel programs that modify shared data in a cachecoherent multiprocessor with a write-invalidate coherence protocol create ownership overhead in the form of ownership acquisitions at writes to shared data. This can have a significant impact on performance in a cache-coherent non-uniform memory architecture (NUMA) multiprocessor. By combining a read-request and an ownership acquisition, the write latency and network traffic can potentially be reduced. In this paper we propose a new hardware-based approach for performing this optimization by targeting load-store sequences, which we show is a super-set of migratory sharing. A loadstore sequence consists of a global read request followed by a global write action to the same memory location from the same processor, without any interveaning access to the same block from any other processor. We use detailed simulation with four benchmark programs including one on-line transaction processing (OLTP) workload and operating system execution...
Jim Nilsson, Fredrik Dahlgren
Added 31 Jul 2010
Updated 31 Jul 2010
Type Conference
Year 2000
Where IPPS
Authors Jim Nilsson, Fredrik Dahlgren
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