Sciweavers
Explore
Publications
Books
Software
Tutorials
Presentations
Lectures Notes
Datasets
Labs
Conferences
Community
Upcoming
Conferences
Top Ranked Papers
Most Viewed Conferences
Conferences by Acronym
Conferences by Subject
Conferences by Year
Tools
Sci2ools
International Keyboard
Graphical Social Symbols
CSS3 Style Generator
OCR
Web Page to Image
Web Page to PDF
Merge PDF
Split PDF
Latex Equation Editor
Extract Images from PDF
Convert JPEG to PS
Convert Latex to Word
Convert Word to PDF
Image Converter
PDF Converter
Community
Sciweavers
About
Terms of Use
Privacy Policy
Cookies
Free Online Productivity Tools
i2Speak
i2Symbol
i2OCR
iTex2Img
iWeb2Print
iWeb2Shot
i2Type
iPdf2Split
iPdf2Merge
i2Bopomofo
i2Arabic
i2Style
i2Image
i2PDF
iLatex2Rtf
Sci2ools
5
click to vote
JOLPE
2006
favorite
Email
discuss
report
38
views
more
JOLPE 2006
»
Reducing Power Dissipation in SRAM during Test
13 years 5 months ago
Download
eprints.ecs.soton.ac.uk
Luigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hash
Real-time Traffic
JOLPE 2006
|
claim paper
Related Content
»
Reduction of Power Dissipation during Scan Testing by Test Vector Ordering
»
Minimizing test power in SRAM through reduction of precharge activity
»
ATPG for Heat Dissipation Minimization During Scan Testing
»
A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limite...
»
Low Power Illinois Scan Architecture for Simultaneous Power and Test Data Volume Reduction
»
Static Compaction Techniques to Control Scan Vector Power Dissipation
»
Simultaneous Reduction of Dynamic and Static Power in Scan Structures
»
Reducing power in superscalar processor caches using subbanking multiple line buffers and ...
»
A 2port 6T SRAM bitcell design with multiport capabilities at reduced area overhead
more »
Post Info
More Details (n/a)
Added
13 Dec 2010
Updated
13 Dec 2010
Type
Journal
Year
2006
Where
JOLPE
Authors
Luigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hashimi, Patrick Girard
Comments
(0)
Researcher Info
JOLPE 2006 Study Group
Computer Vision