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HPCA
2004
IEEE

Reducing the Scheduling Critical Cycle Using Wakeup Prediction

14 years 4 months ago
Reducing the Scheduling Critical Cycle Using Wakeup Prediction
For highest performance, a modern microprocessor must be able to determine if an instruction is ready in the same cycle in which it is to be selected for execution. This creates a cycle of logic involving wakeup and select. However, the time a static instruction spends waiting for wakeup shows little dynamic variance. This idea is used to build a machine where wakeup times are predicted, and instructions executed too early are replayed. This form of self-scheduling reduces the critical cycle by eliminating the wakeup logic at the expense of additional replays. However, replays and other pipeline effects affect the cost of misprediction. To solve this, an allowance is added to the predicted wakeup time to decrease the probability of a replay. This allowance may be associated with individual instructions or the global state, and is dynamically adjusted by a gradient-descent minimum-searching technique. When processor load is low, prediction may be more aggressive ? increasing the chance...
Todd E. Ehrhart, Sanjay J. Patel
Added 01 Dec 2009
Updated 01 Dec 2009
Type Conference
Year 2004
Where HPCA
Authors Todd E. Ehrhart, Sanjay J. Patel
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