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2016

Reducing Switching Latency and Energy in STT-MRAM Caches With Field-Assisted Writing

4 years 10 months ago
Reducing Switching Latency and Energy in STT-MRAM Caches With Field-Assisted Writing
Abstract—A field-assisted spin-torque transfer magnetoresistive RAM (STT-MRAM) cache is presented for the use in high-performance energy-efficient microprocessors. Adding field assistance reduces the switching latency by a factor of 4. An array model is developed to evaluate the switching energy for different field currents and array sizes. Several STT-MRAM-based cells demonstrate a 55% energy reduction as compared with an SRAM cache subsystem. As compared with STT-MRAM caches with subbank buffering and differential writes, a field-assisted STT-MRAM cache improves the system performance by 28%, with a 6.7% increase in energy.
Ravi Patel, Xiaochen Guo, Qing Guo, Engin Ipek, Eb
Added 11 Apr 2016
Updated 11 Apr 2016
Type Journal
Year 2016
Where TVLSI
Authors Ravi Patel, Xiaochen Guo, Qing Guo, Engin Ipek, Eby G. Friedman
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