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TCAD
2008

Register File Power Reduction Using Bypass Sensitive Compiler

8 years 11 months ago
Register File Power Reduction Using Bypass Sensitive Compiler
This paper explores, develops, and investigates several bypass-sensitive compilation techniques to reduce the register file power by reducing the access frequency to the register file. We study the effectiveness of our techniques on the Intel XScale processor, which is based on the previously proposed "on-demand register fetch read" architectural feature. Furthermore, we show that our bypass-sensitive compilation technique is effective on various partial bypass configurations.
Sanghyun Park, Aviral Shrivastava, Nikil D. Dutt,
Added 15 Dec 2010
Updated 15 Dec 2010
Type Journal
Year 2008
Where TCAD
Authors Sanghyun Park, Aviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek, Eugene Earlie
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