Register File Power Reduction Using Bypass Sensitive Compiler

This paper explores, develops, and investigates several bypass-sensitive compilation techniques to reduce the register file power by reducing the access frequency to the register file. We study the effectiveness of our techniques on the Intel XScale processor, which is based on the previously proposed "on-demand register fetch read" architectural feature. Furthermore, we show that our bypass-sensitive compilation technique is effective on various partial bypass configurations.

• Type: Journal
• Year: 2008
• Where: TCAD
• Authors: Sanghyun Park, Aviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek, Eugene Earlie
• Keywords: Bypass-sensitive Compilation Technique, Register File, Register File Power, TCAD 2008