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DATE
2009
IEEE

Reliability aware through silicon via planning for 3D stacked ICs

9 years 5 months ago
Reliability aware through silicon via planning for 3D stacked ICs
Abstract—This work proposes reliability aware through silicon via (TSV) planning for the 3D stacked silicon integrated circuits (ICs). The 3D power distribution network is modeled and extracted in frequency domain which includes the impact of skin effect. The worst case power noise of the 3D power delivery networks (PDN) with local TSV failures resulting from fabrication process or circuit operation is identified in both frequency and time domain. From the experimental results, it is observed that a single TSV failure could increase the maximum voltage variation up to 70% which should be considered in nanoscale ICs. The parameters of the 3D PDN are designed such that the power distribution is reliable under local TSV failures. The spatial distribution of the power noise, reliability and block out area is analyzed to enhance the reliability of the 3D PDN
Amirali Shayan Arani, Xiang Hu, He Peng, Chung-Kua
Added 20 May 2010
Updated 20 May 2010
Type Conference
Year 2009
Where DATE
Authors Amirali Shayan Arani, Xiang Hu, He Peng, Chung-Kuan Cheng, Wenjian Yu, Mikhail Popovich, Thomas Toms, Xiaoming Chen
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