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ENGL
2007

Reordering Algorithm for Minimizing Test Power in VLSI Circuits

8 years 10 months ago
Reordering Algorithm for Minimizing Test Power in VLSI Circuits
— Power consumption has become a crucial concern in Built In Self Test (BIST) due to the switching activity in the circuit under test(CUT). In this paper we present a novel method which aims at minimizing the total power consumption during testing. This is achieved by minimizing the switching activity in the circuit by reducing the Hamming Distance between successive test vectors. In this method the test vectors are reordered for minimum total hamming distance and the same vector set is used for testing. Experimental results with ISCAS benchmark circuits show that the switching activity can be reduced up to 21 % in comparison with conventional ATPG Algorithms like DEFGEN. The Switching activity is reduced significantly when compared with existing methods.
K. Paramasivam, K. Gunavathi
Added 13 Dec 2010
Updated 13 Dec 2010
Type Journal
Year 2007
Where ENGL
Authors K. Paramasivam, K. Gunavathi
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