A retargetable micro-architecture simulator

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A retargetable micro-architecture simulator
The capability of performing architectural exploration has become essential for embedded microprocessor design in System-On-Chip. While many retargetable instruction set (ISA) simulators have been reported, the more relevant micro-architecture simulators, which are capable of modeling the detailed machine features such as cache organization, branch prediction and out-of-order scheduler, have not be equipped with retargetability. In this paper, we propose a new methodology that can generate completed micro-architecture simulators from the abstract ISA and the application binary interface (ABI) specification. We demonstrate our methodology by the development of a tool that can automatically port the SimpleScalar toolset, the de facto standard for micro-architecture simulation , to any processor. Categories and Subject Descriptors I.6.7 [Simulation Support Systems]: Environments; C.0 [General]: Modeling of computer architecture General Terms Design, Languages
Wai Sum Mong, Jianwen Zhu
Added 13 Nov 2009
Updated 13 Nov 2009
Type Conference
Year 2003
Where DAC
Authors Wai Sum Mong, Jianwen Zhu
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