Reviewing 4-to-2 Adders for Multi-Operand Addition

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Reviewing 4-to-2 Adders for Multi-Operand Addition
Recently there has been quite a number of papers discussing the use of redundant 4-to-2 adders for the accumulation of partial products in multipliers, claiming one type to be superior to other types. This paper analyses the use of various 3- and 4-element redundant digit sets for radix 2, and compare their adder implementations using various encodings of the digits and carries. It is shown that theoretically they are equivalent, and differences in their implementations need only be very marginal. Another recent proposal for the use of the digit-set ¼ ½ ¾ ¿ , with a special 3-bit encoding of digits, is analyzed and some optimizations are shown, including the possibility of using a 2-bit encoding, simplifying the wiring of a multiplier tree. All these proposed designs are shown to be equivalent to a standard 4-to-2, carry-save adder, except possibly for a few signal inversions. ½º ÁÒØÖÓ Ù Ø ÓÒ When implementing fast multipliers in VLSI, a major part of area and time is s...
Peter Kornerup
Added 14 Jul 2010
Updated 14 Jul 2010
Type Conference
Year 2002
Where ASAP
Authors Peter Kornerup
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