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DAC
2001
ACM

Route Packets, Not Wires: On-Chip Interconnection Networks

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Route Packets, Not Wires: On-Chip Interconnection Networks
Using on-chip interconnection networks in place of ad-hoc global wiring structures the top level wires on a chip and facilitates modular design. With this approach, system modules (processors, memories, peripherals, etc...) communicate by sending packets to one another over the network. The structured network wiring gives well-controlled electrical parameters that eliminate timing iterations and enable the use of high-performance circuits to reduce latency and increase bandwidth. The area overhead required to implement an on-chip network is modest, we estimate 6.6%. This paper introduces the concept of on-chip networks, sketches a simple network, and discusses some challenges in the architecture and design of these networks.
William J. Dally, Brian Towles
Added 13 Nov 2009
Updated 13 Nov 2009
Type Conference
Year 2001
Where DAC
Authors William J. Dally, Brian Towles
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