Router designs for elastic buffer on-chip networks

This paper explores the design space of elastic buffer (EB) routers by evaluating three representative designs. We propose an enhanced two-stage EB router which maximizes throughput by achieving a 42% reduction in cycle time and 20% reduction in occupied area by using look-ahead routing and replacing the three-slot output EBs in the baseline router of [17] with two-slot EBs. We also propose a singlestage router which merges the two pipeline stages to avoid pipelining overhead. This design reduces zero-load latency by 24% compared to the enhanced two-stage router if both are operated at the same clock frequency; moreover, the single-stage router reduces the required energy per transferred bit and occupied area by 29% and 30% respectively, compared to the enhanced two-stage router. However, the cycle time of the enhanced two-stage router is 26% smaller than that of the single-stage router. Categories and Subject Descriptors B.4.3 [Hardware]: Input/output and data communications—

• Type: Conference
• Year: 2009
• Where: SC
• Authors: George Michelogiannakis, William J. Dally
• Keywords: Applied Computing, Enhanced Two-stage Router, Router, SC 2009, Two-stage Eb Router