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ICCD
2006
IEEE

RTL Scan Design for Skewed-Load At-speed Test under Power Constraints

12 years 8 months ago
RTL Scan Design for Skewed-Load At-speed Test under Power Constraints
This paper discusses an automated method to build scan chains at the register-transfer level (RTL) for powerconstrained at-speed testing. By analyzing a circuit at the RTL, where design complexity is lower than at the gate netlist level, one can divide a circuit into multiple partitions, which can be tested independently in order to reduce test power. Despite activating one partition at a time, we show how through conscious construction of scan chains, high transition fault coverage can be achieved, while reducing test time of the circuit when employing third party test generation tools. Furthermore, as shown in experimental results, by constructing scan chains for the partitioned circuit at the RTL, area and performance penalty of the design-for-test hardware may be reduced.
Ho Fai Ko, Nicola Nicolici
Added 16 Mar 2010
Updated 16 Mar 2010
Type Conference
Year 2006
Where ICCD
Authors Ho Fai Ko, Nicola Nicolici
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