Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis

Abstract. Layout tools for FPGAs can typically be run in two different modes: non-timing-driven and timing-driven. Non-timing-driven mode produces a solution quickly, without consideration of design performance. Timing-driven mode requires that a designer specify performance constraints and then produces a performance-optimized layout solution. The task of generating constraints is burdensome since design performance is difficult to gauge at the pre-layout stage and the relationship between the constraints supplied and tool execution time is unpredictable. In this paper, we propose a new mode for layout tools, called “automatic timing-driven” mode that produces a performance-optimized layout, without requiring any constraint specification. A key feature of this mode is a novel and practical method for automatic constraint generation that creates constraints that result in predictable and controlled layout execution time. The automatic constraint generation approach has been integr...

• Type: Conference
• Year: 2004
• Where: FPL
• Authors: Jason Helge Anderson, Sudip Nag, Kamal Chaudhary, Sandor Kalman, Chari Madabhushi, Paul Cheng
• Keywords: FPL 2004, Layout Tools, Mode, Performance-optimized Layout