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ARCS
2006
Springer

Scalable and Partitionable Asynchronous Arbiter for Micro-threaded Chip Multiprocessors

10 years 5 months ago
Scalable and Partitionable Asynchronous Arbiter for Micro-threaded Chip Multiprocessors
Abstract. This paper presents a scalable and partitionable asynchronous bus arbiter for use with chip multiprocessors (CMP) and its corresponding pre-layout simulation results using VHDL. The arbiter exploits the advantage of a concurrency control instruction (Brk) provided by the micro-threaded microprocessor model to set the priority processor and move the circulated arbitration token at the most likely processor to issue the create instruction. This mechanism provides latency hiding during token circulation by decoupling the micro-threaded processor from the ring's timing. It is shown that this arbiter can be extended easily to support large numbers of processors and can be used for chip multiprocessor arbitration purposes.
Nabil Hasasneh, Ian Bell, Chris R. Jesshope
Added 20 Aug 2010
Updated 20 Aug 2010
Type Conference
Year 2006
Where ARCS
Authors Nabil Hasasneh, Ian Bell, Chris R. Jesshope
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