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2007
IEEE

Scalable Multi-FPGA Platform for Networks-On-Chip Emulation

9 years 11 months ago
Scalable Multi-FPGA Platform for Networks-On-Chip Emulation
Interconnect validation is an important early step toward global SoC (System-On-Chip) validation. Fast performances evaluation and design space exploration for NoCs (Networks-On-Chip) are therefore becoming critical issues. A significant speedup of the global validation process for NoC-centric SoCs could be achieved by prototyping such systems on reconfigurable devices (FPGA). However, as SoC complexity increases with the technology scaling, existing general purpose prototyping platforms are far from being suited for large systems. In this paper we present a study for a scalable multi-FPGA platform, designed for NoCs emulation and debugging. This platform allows the integration of complete systems as well as a near cycleaccurate performance estimation.
Abdellah-Medjadji Kouadri-Mostefaoui, Benaoumeur S
Added 18 Oct 2010
Updated 18 Oct 2010
Type Conference
Year 2007
Where ASAP
Authors Abdellah-Medjadji Kouadri-Mostefaoui, Benaoumeur Senouci, Frédéric Pétrot
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