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2004
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Scalable selective re-execution for EDGE architectures

9 years 3 months ago
Scalable selective re-execution for EDGE architectures
Pipeline flushes are becoming increasingly expensive in modern microprocessors with large instruction windows and deep pipelines. Selective re-execution is a technique that can reduce the penalty of mis-speculations by re-executing only instructions affected by the mis-speculation, instead of all instructions. In this paper we introduce a new selective re-execution mechanism that exploits the properties of a dataflow-like Explicit Data Graph Execution (EDGE) architecture to support efficient mis-speculation recovery, while scaling to window sizes of thousands of instructions with high performance. This distributed selective re-execution (DSRE) protocol permits multiple speculative waves of computation to be traversing a dataflow graph simultaneously, with a commit wave propagating behind them to ensure correct execution. We evaluate one application of this protocol to provide efficient recovery for load-store dependence speculation. Unlike traditional dataflow architectures which...
Rajagopalan Desikan, Simha Sethumadhavan, Doug Bur
Added 30 Jun 2010
Updated 30 Jun 2010
Type Conference
Year 2004
Where ASPLOS
Authors Rajagopalan Desikan, Simha Sethumadhavan, Doug Burger, Stephen W. Keckler
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