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DAC
2008
ACM

Scan chain clustering for test power reduction

9 years 3 months ago
Scan chain clustering for test power reduction
An effective technique to save power during scan based test is to switch off unused scan chains. The results obtained with this method strongly depend on the mapping of scan flip-flops into scan chains, which determines how many chains can be deactivated per pattern. In this paper, a new method to cluster flip-flops into scan chains is presented, which minimizes the power consumption during test. It is not dependent on a test set and can improve the performance of any test power reduction technique consequently. The approach does not specify any ordering inside the chains and fits seamlessly to any standard tool for scan chain integration. The application of known test power reduction techniques to the optimized scan chain configurations shows significant improvements for large industrial circuits. Categories and Subject Descriptors B.8.1 [Hardware]: Performance and Reliability - Reliability, Testing and Fault-Tolerance General Terms Algorithms, Reliability Keywords Test, Design for T...
Christian G. Zoellin, Hans-Joachim Wunderlich, Jen
Added 12 Nov 2009
Updated 12 Nov 2009
Type Conference
Year 2008
Where DAC
Authors Christian G. Zoellin, Hans-Joachim Wunderlich, Jens Leenstra, Melanie Elm, Michael E. Imhof, Nicolas Mäding
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