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ITC
2002
IEEE

Scan Power Reduction Through Test Data Transition Frequency Analysis

10 years 3 months ago
Scan Power Reduction Through Test Data Transition Frequency Analysis
Significant reductions in test application times can be achieved through parallelizing core tests; however, simultaneous test of various cores may result in exceeding power thresholds, endangering the SOC being tested. Test power dissipation is exceedingly high in scan-based environments wherein scan chain transitions during the shift of test data further reflect into significant levels of circuit switching unnecessarily. Scan chain modification helps mitigate this problem as it enables the reduction of transitions in the test stimuli to be inserted to the modified scan chain and in the response to be collected through the scan-out pin. The proposed modifications in the scan chain consist of inverter insertion and scan cell reordering, leading to significant power reductions with neither area nor performance penalty whatsoever. A computationally efficient algorithm is presented to identify the optimal scan chain modification based on the transition frequency analysis of the t...
Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailog
Added 15 Jul 2010
Updated 15 Jul 2010
Type Conference
Year 2002
Where ITC
Authors Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu
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