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8

FPL
2004
Springer

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Secure Logic Synthesis

13 years 9 months ago

Secure Logic Synthesis

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This paper describes the synthesis of dynamic differential logic to increase the resistance of FPGAs against Differential Power Analysis. Compared with an existing technique, it saves more than a factor 2 in slice utilization. Experimental results indicate that a secure version of the AES algorithm can now be implemented with a mere doubling of the slice utilization when compared with a normal non-secure single ended implementation.

Kris Tiri, Ingrid Verbauwhede

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FPL 2004 | Mere Doubling | Single Ended Implementation | Slice Utilization |

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Added	01 Jul 2010
Updated	01 Jul 2010
Type	Conference
Year	2004
Where	FPL
Authors	Kris Tiri, Ingrid Verbauwhede

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