Secure Memory Accesses on Networks-on-Chip

12 years 1 months ago
Secure Memory Accesses on Networks-on-Chip
Security is gaining relevance in the development of embedded devices. Toward a secure system at each level of design, this paper addresses security aspects related to Network-on-Chip (NoC) architectures, foreseen as the communication infrastructure of next-generation embedded devices. In the context of NoC-based multiprocessor systems, we focus on the topic, not yet thoroughly faced, of data protection. In this paper, we present a secure NoC architecture composed of a set of Data Protection Units (DPUs) implemented within the Network Interfaces (NIs). The runtime configuration of the programmable part of the DPUs is managed by a central unit, the Network Security Manager (NSM). The DPU, similar to a firewall, can check and limit the access rights (none, read, write, or both) of processors accessing data and instructions in a shared memory. In particular, the DPU can distinguish between the operating roles (supervisor/user and secure/nonsecure) of the processing elements. We explore alt...
Leandro Fiorin, Gianluca Palermo, Slobodan Lukovic
Added 15 Dec 2010
Updated 15 Dec 2010
Type Journal
Year 2008
Where TC
Authors Leandro Fiorin, Gianluca Palermo, Slobodan Lukovic, V. Catalano, Cristina Silvano
Comments (0)