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DFT
2006
IEEE

Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead

9 years 7 months ago
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores designed according to the IEEE 1500 standard. The system spares memory and keeps acceptable test access mechanism requirements. The diagnostic system uses a built-in processor for test control, the embedded RAM memory for storing both the compressed test vectors and the partial reconfiguration bit streams and the FPGA (Fieldprogrammable gate array) part of the chip for the wrapped cores implementation. The highly compressed test vectors are transferred from the memory to those selected cores that are reconfigured into the embedded tester cores. The patterns are decompressed within the internal scan chains of the embedded tester cores and they are simultaneously fed into the parallel scan chains of the cores under test through Test Access Mechanism (TAM) and standard wrappers. After having tested the first core...
Ondrej Novák, Zdenek Plíva, Jiri Jen
Added 11 Jun 2010
Updated 11 Jun 2010
Type Conference
Year 2006
Where DFT
Authors Ondrej Novák, Zdenek Plíva, Jiri Jenícek, Zbynek Mader, Michal Jarkovský
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