Self-Timed Architecture of a Reduced Instruction Set Computer

An advanced Self-Timed Reduced Instruction Set Computer (ST-RISC) architecture is described. It is designed hierarchically, and is formally specified functionally at the various levels by a CSP-like language. The architectural features include decoupled data and branch processors, delayed branches with variable delay, unified data path and control, efficient non-redundant handshaking protocols, and novel self-timed building blocks such as combinational logic, master-slave registers, finite state machines, and FIFO elements.

• Type: Conference
• Year: 1993
• Where: IFIP
• Authors: Ilana David, Ran Ginosar, Michael Yoeli
• Keywords: IFIP 1993, Non-redundant Handshaking Protocols, Programming Languages, Self-timed Building Blocks, Self-Timed Reduced Instruction