Self-Timed Ring for Globally-Asynchronous Locally-Synchronous Systems

The lack of proven mechanisms for transferring data between multiple synchronous islands has been a major impediment for applying globally asynchronous locally synchronous (GALS) techniques to SoC design. We have implemented on a VLSI test chip three alternative solutions to fill the gap: an arbitrated bus, a switch, and a self-timed ring. Circuit details and various extensions of the basic ring structure are also being discussed. These include bypassing ring transceivers to free the local islands from managing en route traffic and transceivers that inform the sender in case a defective receiver is unable to accept a data item. This is indispensable to prevent any deadlocks. For a ring with five nodes a total data throughput of 520 MegaDataPackets/s was achieved.

• Type: Conference
• Year: 2003
• Where: ASYNC
• Authors: Thomas Villiger, Hubert Kaeslin, Frank K. Gürkaynak, Stephan Oetiker, Wolfgang Fichtner
• Keywords: ASYNC 2003, Basic Ring Structure, Hardware, Multiple Synchronous Islands, VLSI Test Chip