Sciweavers

Share
GLVLSI
2006
IEEE

Sensitivity evaluation of global resonant H-tree clock distribution networks

10 years 2 months ago
Sensitivity evaluation of global resonant H-tree clock distribution networks
A sensitivity analysis of resonant H-tree clock distribution networks is presented in this paper for a TSMC 0.18 μm CMOS technology. The analysis focuses on the effect of the driving buffer output resistance, on-chip inductor and capacitor size, and signal and shielding transmission line width and spacing on the output voltage swing and power consumption. A two level resonant H-tree network exhibits low sensitivity to these variations. Categories and Subject Descriptors B.7.1 [Integrated Circuits]: Types and Design Styles – Advanced technologies, VLSI (very large scale integration). General Terms Design. Keywords Resonance, clock distribution networks, on-chip inductors and capacitors, H-tree sector, sensitivity.
Jonathan Rosenfeld, Eby G. Friedman
Added 11 Jun 2010
Updated 11 Jun 2010
Type Conference
Year 2006
Where GLVLSI
Authors Jonathan Rosenfeld, Eby G. Friedman
Comments (0)
books