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VLSISP
2008

Serial and Parallel FPGA-based Variable Block Size Motion Estimation Processors

8 years 6 months ago
Serial and Parallel FPGA-based Variable Block Size Motion Estimation Processors
H.264/AVC is the latest video coding standard adopting variable block size motion estimation (VBS-ME), quarter-pixel accuracy, motion vector prediction and multi-reference frames for motion estimation. These new features result in much higher computation requirements than previous coding standards. In this paper we propose a novel most significant bit (MSB) first bit-serial architecture for full-search block matching VBS-ME, and compare it with systolic implementations. Since the nature of MSB-first processing enables early termination of the sum of absolute difference (SAD) calculation, the average hardware performance can be enhanced. Five different designs, one and two dimensional systolic and tree implementations along with bitserial, are compared in terms of performance, pixel memory bandwidth, occupied area and power consumption.
Brian M. H. Li, Philip Heng Wai Leong
Added 16 Dec 2010
Updated 16 Dec 2010
Type Journal
Year 2008
Where VLSISP
Authors Brian M. H. Li, Philip Heng Wai Leong
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