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ASPDAC
2007
ACM

Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores

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Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores
Abstract-- This paper proposes a novel power-aware multifrequency wrapper architecture design to achieve at-speed testability. The trade-offs between power dissipation, scan time and bandwidth are well handled by gating off certain virtual cores at a time while parallelizing the remaining. A shelf packing based optimization algorithm is proposed to design and optimize the wrapper architecture while minimizing the test time under power and bandwidth constraints.
Dan Zhao, Unni Chandran, Hideo Fujiwara
Added 13 Aug 2010
Updated 13 Aug 2010
Type Conference
Year 2007
Where ASPDAC
Authors Dan Zhao, Unni Chandran, Hideo Fujiwara
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