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2010
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On Signal Tracing for Debugging Speedpath-Related Electrical Errors in Post-Silicon Validation

9 years 9 months ago
On Signal Tracing for Debugging Speedpath-Related Electrical Errors in Post-Silicon Validation
One of the most challenging problems in post-silicon validation is to identify those errors that cause prohibitive extra delay on speedpaths in the circuit under debug (CUD) and only expose themselves in a certain electrical environment. To address this problem, we propose a trace-based silicon debug solution, which provides real-time visibility to the speedpaths in the CUD during normal operation. Since tracing all speedpath-related signals can cause prohibited design for debug (DfD) overhead, we present an automated trace signal selection methodology that maximizes error detection probability under a given constraint. In addition, we develop a novel trace qualification technique that reduces the storage requirement in trace buffers. The effectiveness of the proposed methodology is verified with large benchmark circuits.
Xiao Liu, Qiang Xu
Added 10 Feb 2011
Updated 10 Feb 2011
Type Journal
Year 2010
Where ATS
Authors Xiao Liu, Qiang Xu
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