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2012
Springer

A Signature-Based Power Model for MPSoC on FPGA

7 years 3 months ago
A Signature-Based Power Model for MPSoC on FPGA
e technique is based on abstract execution profiles, called event signatures, and it operates at a higher level of abstraction than, for example, commonly used instruction-set simulator (ISS)-based power estimation methods and should thus be capable of achieving good evaluation performance. As a consequence, the technique can be very useful in the context of early systemlevel design space exploration. We integrated the power estimation technique in a system-level MPSoC synthesis framework. Subsequently, using this framework, we designed a range of different candidate architectures which contain different numbers of MicroBlaze processors and compared our power estimation results to those from real measurements on a Virtex-6 FPGA board.
Roberta Piscitelli, Andy D. Pimentel
Added 25 Apr 2012
Updated 25 Apr 2012
Type Journal
Year 2012
Where VLSI
Authors Roberta Piscitelli, Andy D. Pimentel
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