Sciweavers

Share
SPAA
2010
ACM

Simplifying concurrent algorithms by exploiting hardware transactional memory

12 years 6 months ago
Simplifying concurrent algorithms by exploiting hardware transactional memory
We explore the potential of hardware transactional memory (HTM) to improve concurrent algorithms. We illustrate a number of use cases in which HTM enables significantly simpler code to achieve similar or better performance than existing algorithms for conventional architectures. We use Sun’s prototype multicore chip, codenamed Rock, to experiment with these algorithms, and discuss ways in which its limitations prevent better results, or would prevent production use of algorithms even if they are successful. Our use cases include concurrent data structures such as double ended queues, work stealing queues and scalable non-zero indicators, as well as a scalable malloc implementation and a simulated annealing application. We believe that our paper makes a compelling case that HTM has substantial potential to make effective concurrent programming easier, and that we have made valuable contributions in guiding designers of future HTM features to exploit this potential.
Dave Dice, Yossi Lev, Virendra J. Marathe, Mark Mo
Added 18 Jul 2010
Updated 18 Jul 2010
Type Conference
Year 2010
Where SPAA
Authors Dave Dice, Yossi Lev, Virendra J. Marathe, Mark Moir, Daniel Nussbaum, Marek Olszewski
Comments (0)
books