Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment

This paper presents a new test methodology which utilizes the Programming Language Interface (PLI) for performing fault simulation of combinational or full scan Intellectual Property (IP) core-based designs for System-on-Chip (SOC). Using the latest Verilog PLI, referred to as Verilog Procedural Interface (VPI), critical-path tracing and two-value deductive fault simulations are performed on a pre-compiled core basis as available in a simulator s intermediate format. By applying this VPI-based test methodology on ISCAS85 Verilog benchmarks results are presented in terms of elapsed simulation time and fault coverage for stuck-at faults and improvement over previous works is reported.

• Type: Conference
• Year: 2005
• Where: DFT
• Authors: Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi
• Keywords: DFT 2005, Fault Simulations, Hardware, Latest Verilog Pli, Verilog Procedural Interface