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DATE
2004
IEEE

A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design

10 years 3 months ago
A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design
We present the design exploration of a System-on-Chip architecture dedicated to the implementation of the HIPERLAN/2 communication protocol. The task was accomplished by means of an ad-hoc C++ simulation environment, integrating power models for CPUs, memories and buses used in the design and incorporating software profiling capabilities. The architecture is based on two ARM microprocessors, an AMBA bus and a local bus, DMA unit and other peripherals. Software mapping on the processor has been based on the power/performance profiling results.
Francesco Menichelli, Mauro Olivieri, Luca Benini,
Added 20 Aug 2010
Updated 20 Aug 2010
Type Conference
Year 2004
Where DATE
Authors Francesco Menichelli, Mauro Olivieri, Luca Benini, Monica Donno, Labros Bisdounis
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