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2007
IEEE

Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis

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Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis
We present minimization methodologies and an algorithm for simultaneous scheduling, binding, and allocation for the reduction of total power and power fluctuation during behavioral synthesis. We consider resources of dual gate oxide thicknesses, dual threshold voltage, and dual power supply. Statistical variations in these parameters are explicitly taken into account by using Monte Carlo simulations to characterize a datapath component library which is then used during behavioral synthesis. The formulated multi-objective cost function is optimized for various resource and time constraints. We present results on several standard benchmarks where we observed significant reduction in total power (as high as 75% without time penalty) and elimination of total power fluctuation (as high as 76% without time penalty). To the best of the authors' knowledge, this is the first-ever behavioral synthesis work addressing fluctuation in total power consumption accounting for gate and subthresho...
Saraju P. Mohanty, Elias Kougianos
Added 30 Nov 2009
Updated 30 Nov 2009
Type Conference
Year 2007
Where VLSID
Authors Saraju P. Mohanty, Elias Kougianos
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