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GLVLSI
2009
IEEE

Simultaneous shield and repeater insertion

10 years 5 months ago
Simultaneous shield and repeater insertion
Resource based optimization for high performance integrated circuits is presented. The methodology is applied to simultaneous shield and repeater insertion, resulting in minimum coupling noise under power, delay, and area constraints. Design expressions exhibiting parabolic noise behavior are compared with SPICE simulations. Due to the parabolic coupled noise behavior, the minimum noise is established. Good agreement between the analytic results and SPICE simulations is shown. Categories and Subject Descriptors B.7.m [Integrated Circuits]: Miscellaneous—Interconnects, resources General Terms Design Keywords Interconnects, area, delay, noise, power
Renatas Jakushokas, Eby G. Friedman
Added 21 May 2010
Updated 21 May 2010
Type Conference
Year 2009
Where GLVLSI
Authors Renatas Jakushokas, Eby G. Friedman
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