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JCP
2008

Simultaneous Sleep Transistor Insertion and Power Network Synthesis for Industrial Power Gating Designs

8 years 12 months ago
Simultaneous Sleep Transistor Insertion and Power Network Synthesis for Industrial Power Gating Designs
Sleep transistors in industrial power-gating designs are custom designed with an optimal size. Consequently, sleep transistor P/G network optimization becomes a problem of finding the optimal number of sleep transistors and their placement as well as optimal P/G network grids, wire widths and layers. This paper presents a fake via based sleep transistor P/G network synthesis method, which addresses the requirements from industrial power-gating designs. The method produces optimal sleep transistor P/G networks by simultaneously optimizing sleep transistor insertion and placement as well as the power network grids and wires for minimum area, maximum routability with a given IR-drop target.
Kaijian Shi, Zhian Lin, Yi-Min Jiang, Lin Yuan
Added 13 Dec 2010
Updated 13 Dec 2010
Type Journal
Year 2008
Where JCP
Authors Kaijian Shi, Zhian Lin, Yi-Min Jiang, Lin Yuan
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