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15

SEUS
2009
IEEE

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A Single-Path Chip-Multiprocessor System

13 years 11 months ago

A Single-Path Chip-Multiprocessor System

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Abstract. In this paper we explore the combination of a time-predictable chipmultiprocessor system with the single-path programming paradigm. Time-sliced arbitration of the main memory access provides time-predictable memory load and store instructions. Single-path programming avoids control ﬂow dependent timing variations. To keep the execution time of tasks constant, even in the case of shared memory access of several processor cores, the tasks on the cores are synchronized with the time-sliced memory arbitration unit.

Martin Schoeberl, Peter P. Puschner, Raimund Kirne

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Embedded Systems | Main Memory Access | Memory Access | SEUS 2009 | Time-predictable Memory Load |

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Added	21 May 2010
Updated	21 May 2010
Type	Conference
Year	2009
Where	SEUS
Authors	Martin Schoeberl, Peter P. Puschner, Raimund Kirner

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