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1996
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Size-Constrained Code Placement for Cache Miss Rate Reduction

9 years 6 months ago
Size-Constrained Code Placement for Cache Miss Rate Reduction
In design of an embedded system with a cache, it is important to minimize the cache miss rate to reduce the power consumption as well as to improvethe performance of the system. We have previously proposed a code placement method which minimizes miss rates of instruction caches [10], but it makes code size larger. In most cases, code size is a tight design constraint. In this paper, we propose a size-constrained code placement method which minimizes cache miss rates under constraint on code size given by system designers. Experimental results show that the sizeconstrained code placement method achieves 36% decrease
Hiroyuki Tomiyama, Hiroto Yasuura
Added 07 Aug 2010
Updated 07 Aug 2010
Type Conference
Year 1996
Where ISSS
Authors Hiroyuki Tomiyama, Hiroto Yasuura
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