Slack redistribution for graceful degradation under voltage overscaling

Modern digital IC designs have a critical operating point, or "wall of slack", that limits voltage scaling. Even with an errortolerance mechanism, scaling voltage below a critical voltage - so-called overscaling - results in more timing errors than can be effectively detected or corrected. This limits the effectiveness of voltage scaling in trading off system reliability and power. We propose a designlevel approach to trading off reliability and voltage (power) in, e.g., microprocessor designs. We increase the range of voltage values at which the (timing) error rate is acceptable; we achieve this through techniques for power-aware slack redistribution that shift the timing slack of frequently-exercised, near-critical timing paths in a power- and area-efficient manner. The resulting designs heuristically minimize the voltage at which the maximum allowable error rate is encountered, thus minimizing power consumption for a prescribed maximum error rate and allowing the design to...

• Type: Journal
• Year: 2010
• Where: ASPDAC
• Authors: Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori
• Keywords: ASPDAC 2010, Designs, Error Rate, Hardware, Voltage