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IJCSA
2008

A Smart Architecture for Low-Level Image Computing

13 years 3 months ago
A Smart Architecture for Low-Level Image Computing
This paper presents a comparison relating two different vision system architectures. The first one involves a smart sensor including analog processors allowing on-chip image processing. An external microprocessor is used to control the on-chip dataflow and integrated operators. The second system implements a logarithmic CMOS/APS sensor interfaced to the same microprocessor, in which all computations are carried out. We have designed two vision systems as proof-of-concept. The comparison is related to image processing time. Results reveal that one of the solutions to resolve the computational complexity of computer vision algorithms is to perform some low-level image processing on the sensor focal plane. This concept makes the vision systems more compact as a system on chip and increases performance thanks to the reduction of dataflow exchanges, with external circuits, and power consumption. Keywords Vision systems architecture; smart sensors; Image processing.
A. Elouardi, Samir Bouaziz, Antoine Dupret, Lionel
Added 12 Dec 2010
Updated 12 Dec 2010
Type Journal
Year 2008
Where IJCSA
Authors A. Elouardi, Samir Bouaziz, Antoine Dupret, Lionel Lacassagne, Jacques-Olivier Klein, Roger Reynaud
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