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Soft error reduction in combinational logic using gate resizing and flipflop selection

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Soft error reduction in combinational logic using gate resizing and flipflop selection
Soft errors in logic are emerging as a significant reliability problem for VLSI designs. This paper presents novel circuit optimization techniques to mitigate soft error rates (SER) of combinational logic circuits. First, we propose a gate sizing algorithm that trades off SER reduction and area overhead. This approach first computes bounds on the maximum achievable SER reduction by resizing a gate. This bound is then used to prune the circuit graph, arriving at a smaller set of candidate gates on which we perform incremental sensitivity computations to determine the gates that are the largest contributors to circuit SER. Second, we propose a flipflop selection method that uses slack information at each primary output node to determine the flipflop configuration that produces maximum SER savings. This approach uses an enhanced flipflop library that contains flipflops of varying temporal masking ability. Third, we propose a unified, cooptimization approach combining flipflop selection w...
Rajeev R. Rao, David Blaauw, Dennis Sylvester
Added 16 Mar 2010
Updated 16 Mar 2010
Type Conference
Year 2006
Where ICCAD
Authors Rajeev R. Rao, David Blaauw, Dennis Sylvester
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