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2005
IEEE

Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits

9 years 26 days ago
Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits
Nanometer circuits are becoming increasingly susceptible to soft-errors due to alpha-particle and atmospheric neutron strikes as device scaling reduces node capacitances and supply/threshold voltage scaling reduces noise margins. It is becoming crucial to add softerror tolerance estimation and optimization to the design flow to handle the increasing susceptibility. The first part of this paper presents a tool for accurate soft-error tolerance analysis of nanometer circuits (ASERTA) that can be used to estimate the soft-error tolerance of nanometer circuits consisting of millions of gates. The tolerance estimates generated by the tool match SPICE generated estimates closely while taking orders of magnitude less computation time. The second part of the paper presents a tool for soft-error tolerance optimization of nanometer circuits (SERTOPT) using the tolerance estimates generated by ASERTA. The tool finds optimal sizes, channel lengths, supply voltages and threshold voltages to be ass...
Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhij
Added 24 Jun 2010
Updated 24 Jun 2010
Type Conference
Year 2005
Where DATE
Authors Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee
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