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2008
IEEE

Software Barrier Performance on Dual Quad-Core Opterons

9 years 5 months ago
Software Barrier Performance on Dual Quad-Core Opterons
Multi-core processors based SMP servers have become building blocks for Linux clusters in recent years because they can deliver better performance for multi-threaded programs through on-chip multi-threading. However, a relative slow software barrier can hinder the performance of a data-parallel scientific application on a multi-core system. In this paper we study the performance of different software barrier algorithms on a server based on newly introduced AMD quad-core Opteron processors. We study how the memory architecture and the cache coherence protocol of the system influence the performance of barrier algorithms. We present an optimized barrier algorithm derived from the queue-based barrier algorithm. We find that
Jie Chen, William A. Watson III
Added 31 May 2010
Updated 31 May 2010
Type Conference
Year 2008
Where IWNAS
Authors Jie Chen, William A. Watson III
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