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2006
IEEE

Software-hardware cooperative memory disambiguation

10 years 7 days ago
Software-hardware cooperative memory disambiguation
In high-end processors, increasing the number of in-flight instructions can improve performance by overlapping useful processing with long-latency accesses to the main memory. Buffering these instructions requires a tremendous amount of microarchitectural resources. Unfortunately, large structures negatively impact processor clock speed and energy efficiency. Thus, innovations in effective and efficient utilization of these resources are needed. In this paper, we target the load-store queue, a dynamic memory disambiguation logic that is among the least scalable structures in a modern microprocessor. We propose to use software assistance to identify load instructions that are guaranteed not to overlap with earlier pending stores and prevent them from competing for the resources in the load-store queue. We show that the design is practical, requiring off-line analyses and minimum architectural support. It is also very effective, allowing more than 40% of loads to bypass the load-store q...
Ruke Huang, Alok Garg, Michael C. Huang
Added 01 Dec 2009
Updated 01 Dec 2009
Type Conference
Year 2006
Where HPCA
Authors Ruke Huang, Alok Garg, Michael C. Huang
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