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FCCM
2006
IEEE

Sparse Matrix-Vector Multiplication for Finite Element Method Matrices on FPGAs

9 years 7 months ago
Sparse Matrix-Vector Multiplication for Finite Element Method Matrices on FPGAs
We present an architecture and an implementation of an FPGA-based sparse matrix-vector multiplier (SMVM) for use in the iterative solution of large, sparse systems of equations arising from Finite Element Method (FEM) applications. The architecture is based on a pipelined linear array of processing elements (PEs). A hardware-oriented matrix “striping” scheme is developed which reduces the number of required processing elements. Our current 8 PE proto
Yousef El-Kurdi, Warren J. Gross, Dennis Giannacop
Added 11 Jun 2010
Updated 11 Jun 2010
Type Conference
Year 2006
Where FCCM
Authors Yousef El-Kurdi, Warren J. Gross, Dennis Giannacopoulos
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